Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction
نویسنده
چکیده
منابع مشابه
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes
Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requi...
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ورودعنوان ژورنال:
- Signal Processing Systems
دوره 79 شماره
صفحات -
تاریخ انتشار 2015